post code master - the site for BIOS, POST & BEEP code information

Home | Products | View Cart | Contact Us

Sun Ultra 27 Workstation BIOS Post Codes

  • 03 - Test CMOS R/W functionality.
  • 04 - Early chipset initialization: Disable shadow RAM. Disable L2 cache (socket 7 or below). Program basic chipset registers.
  • 05 - Detect memory: Auto detection of DRAM size, type, and ECC. Auto detection of L2 cache (socket 7 or below).
  • 06 - Expand compressed BIOS code to DRAM.
  • 07 - Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
  • 08 - Expand the Xgroup codes located in physical address 1000:0.
  • C0 - Reserved.
  • C1 - Initial Superio_Early_Init switch.
  • C2 - Reserved.
  • C5 - 1. Blank out screen. 2. Clear CMOS error flag.
  • C6 - Reserved.
  • C7 - 1. Clear 8042 interface. 2. Initialize 8042 self-test.
  • 0A - 1. Test special keyboard controller for Winbond 977 series Super I/O chips. 2. Enable keyboard interface.
  • 0B - Reserved.
  • 0C - 1. Disable PS/2 mouse interface (optional). 2. Autodetect ports for keyboard and mouse followed by a port and interface swap (optional). 3. Reset keyboard for Winbond 977 series Super I/O chips.
  • 0E - Reserved.
  • 13 - Reserved.
  • 20 - Reserved.
  • 24 - Test F000h segment shadow to see whether it is read/writable or not. If test fails, keep beeping the speaker.
  • 2A - Reserved.
  • 2C - Autodetect flash type to load appropriate flash R/W codes into the runtime area in F000 for ESCD & DMI support.
  • 2E - Reserved.
  • 31 - Use walking 1as algorithm to check out interface in CMOS circuitry. Also, set real-time clock power status, and then check for override.
  • 33 - Reserved.
  • 37 - Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers.
  • 38 - Reserved.
  • 39 - Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26h.
  • 3A - Reserved.
  • 3B - Detect CPU information including brand, SMI type (Cyrix or Intel), and CPU level (586 or 686).
  • 3C - Reserved.
  • 40 - Reserved.
  • 52 - Initial interrupts vector table. All hardware interrupts are directed to SPURIOUS_INT_HDLR and software interrupts to SPURIOUS_soft_HDLR.
  • 60 - Reserved.
  • 75 - Initial EARLY_PM_INIT switch.
  • 78 - Reserved.
  • 7C - Load keyboard matrix (notebook platform).
  • 84 - Reserved.
  • 85 - HPM initialization (notebook platform).
  • 87 - Reserved.
  • 8C - 1. Check validity of RTC value. For example, a value of 5Ah is an invalid value for RTC minute. 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.
  • 8D - Prepare BIOS resource map for PCI and PnP use. If ESCD is valid, consider the ESCD as legacy information.
  • 8E - Early PCI initialization: Enumerate PCI bus number. Assign memory and I/O resource. Search for a valid VGA device and VGA BIOS, and put it into C000:0.
  • 90 - 1. If Early_Init_Onboard_Generator is not defined, Onboard clock generator initialization. Disable respective clock resource to empty ‚PCI and DIMM slots. 2. Initialize onboard PWM. 3. Initialize onboard H/W monitor devices.
  • A1 - Initialize INT 09 buffer.
  • A2 - Reserved.
  • A4 - 1. Program CPU internal MTRR (P6 and PII) for 0?640K memory address. 2. Initialize the APIC for Pentium class CPU. 3. Program early chipset according to CMOS setup. Example: ‚onboard IDE controller. 4. Measure CPU speed.
  • A7 - Reserved.
  • A9 - Invoke video BIOS.
  • AA - Reserved.
  • AB - 1. Initialize double-byte language font (optional). 2. Display information on screen, including award title, CPU type, CPU speed, and full-screen logo.
  • AC - Reserved.
  • B1 - Reserved.
  • 00 - Reserved.
Home | Products | Contact Us | View Cart | © 2012 Microsystems Development Tech. Inc.