post code master - the site for BIOS, POST & BEEP code information

Home | Products | View Cart | Contact Us

Phoenix BIOS 4.0 Post Codes

  • 02 - Verify real mode
  • 04 - Get CPU type
  • 06 - Initialize system hardware
  • 08 - Initialize chipset registers with initial POST values
  • 09 - Set in POST flag
  • 0A - Initialize CPU registers
  • 0C - Initialize cache to initial POST values
  • 0E - Initialize I/O
  • 10 - Initialize power management
  • 11 - Load alternate registers with initial POST values
  • 12 - Jump to User Patch
  • 14 - Initialize keyboard controller
  • 16 - BIOS ROM checksum
  • 18 - 8254 programmable interrupt timer initialization
  • 1A - 8237 DMA controller initialization
  • 1C - Reset 8254 programmable interrupt timer
  • 20 - Test DRAM refresh
  • 22 - Test 8742 keyboard controller
  • 24 - Set ES segment register to 4GB
  • 28 - Autosize DRAM
  • 2A - Clear 512K base RAM
  • 2C - Test 512K base address lines
  • 2E - Test 512K base memory
  • 32 - Test CPU bus-clock frequency
  • 37 - Reinitialize the chipset
  • 38 - Shadow system BIOS ROM
  • 39 - Reinitialize the cache
  • 3A - Autosize cache
  • 3C - Configure advanced chipset registers
  • 3D - Load alternate registers with CMOS values
  • 40 - Set initial CPU speed
  • 42 - Initialize interrupt vectors
  • 44 - Initialize BIOS interrupts
  • 46 - Check ROM copyright notice
  • 48 - Check video configuration against CMOS
  • 49 - Initialize PCI bus and devices
  • 4A - Initialize all video adapters in system
  • 4C - Shadow video BIOS ROM
  • 4E - Display copyright notice
  • 50 - Display CPU type and speed
  • 52 - Test keyboard
  • 54 - Set key click if enabled
  • 56 - Enable keyboard
  • 58 - Test for unexpected interrupts
  • 5A - Display prompt: Press F2 to Enter Setup
  • 5C - Test RAM between 512K and 640K
  • 60 - Test expanded memory
  • 62 - Test extended memory address lines
  • 64 - Jump to UserPatch1
  • 66 - Configure advanced cache registers
  • 68 - Enable external and CPU caches
  • 6A - Display external cache size
  • 6C - Display shadow message
  • 6E - Display non-disposable segments
  • 70 - Display error messages
  • 72 - Check for configuration errors
  • 74 - Test real time clock
  • 76 - Check for keyboard errors
  • 7C - Setup hardware interrupts vectors
  • 7E - Test coprocessor if present
  • 80 - Disable onboard I/O ports
  • 82 - Detect and install external RS232 ports
  • 84 - Detect and install external parallel ports
  • 86 - Re-initialize on-board I/O ports
  • 88 - Initialize BIOS data area
  • 8A - Initialize extended BIOS data area
  • 8C - Initialize floppy controller
  • 90 - Initialize hard disk controller
  • 91 - Initialize local bus hard disk controller
  • 92 - Jump to UserPatch2
  • 94 - Disable A20 address line
  • 96 - Clear huge ES segment register
  • 98 - Search for option ROM's
  • 9A - Shadow option ROM's
  • 9C - Setup power management
  • 9E - Enable hardware interrupts
  • A0 - Set time of day
  • A2 - Check key lock
  • A8 - Erase F2 prompt
  • AA - Scan for F2 keystroke
  • AC - Enter setup
  • AE - Clear in-POST flag
  • B0 - Check for errors
  • B2 - POST done; prepare to boot operating system
  • B4 - One beep
  • B6 - Check password (optional)
  • B8 - clear global descriptor table
  • BC - Clear parity checkers
  • BE - Clear screen (optional)
  • BF - Check virus and backup reminders
  • C0 - Try to boot interrupt 19
  • D0 - Interrupt handler error
  • D2 - Unknown interrupt error
  • D4 - Pending interrupt error
  • D6 - Initialize option ROM error
  • D8 - Shutdown error
  • DA - Extended block move
  • DC - Shutdown 10 error
  • E2 - Initialize the chipset
  • E3 - Initialize refresh counter
  • E4 - Check for forced flash
  • E5 - Check HW status of ROM
  • E6 - BIOS ROM is ok
  • E7 - Do a complete RAM test
  • E8 - Do OEM initialization
  • E9 - Initialize interrupt controller
  • EA - Read in bootstrap code
  • EB - Initialize all vectors
  • EC - Boot the flash program
  • ED - Initialize the boot device
  • EE - Boot code was read ok
Home | Products | Contact Us | View Cart | © 2012 Microsystems Development Tech. Inc.