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Intel L440GX/LB440GX Motherboard BIOS Post Codes

  • 00 - Wait for secondary processor to execute init SMI handler
  • 02 - Verify real mode
  • 04 - Get processor type
  • 06 - Initialize system hardware
  • 08 - Initialize PCI set registers with initial POST values
  • 09 - Set IN POST flag
  • 0A - Initialize processor registers and processor microcode
  • 0B - Enable processor cache
  • 0C - Initialize caches to initial POST values
  • 0E - Initialize I/O
  • 0F - Initialize the local bus IDE (not used anymore but here for Phoenix standard)
  • 10 - Initialize Power Management (APM not used in L440GX+)
  • 11 - Load alternate registers with initial POST values
  • 14 - Initialize keyboard controller
  • 12 - Restore processor control word during warm boot (only occurs on warm boot)
  • 16 - BIOS ROM checksum
  • 17 - Turn cache off
  • 18 - 8254 timer initialization
  • 1A - 8237 DMA controller initialization
  • 1C - Reset programmable interrupt controller (PIC)
  • 20 - Test DRAM refresh
  • 22 - Reset and test keyboard first try (only warm reset)
  • 24 - Put processor in big real mode (flat mode memory addressing - up to 4GB)
  • 28 - Auto-size DRAM
  • 29 - Post Memory Manager initialization (PMM)
  • 2A - Clear 512KB base RAM
  • 2C - RAM failure on address line XXXX
  • 2E - RAM failure on data bits XXXX of low byte of memory bus (1st 4Meg)
  • 2F - Initialize L2 cache if enabled in CMOS
  • 32 - Read processor bus-clock frequency and compute boot processor speed
  • 33 - Post Dispatch Manager initialization
  • 34 - Test CMOS
  • 38 - Shadow system BIOS ROM
  • 3A - Auto-size cache
  • 3C - Configure advanced PCI set registers and reset coprocessor
  • 3D - Load alternate registers with CMOS values
  • 42 - Initialize interrupt vectors
  • 45 - Initialize all pre-PnP devices
  • 46 - Check ROM copyright notice
  • 48 - Check video configuration against CMOS (VGA or MDA)
  • 49 - Initialize PCI bus and devices (also read ESCD and allocate resources)
  • 4A - Initialize all video adapters in system
  • 4C - Shadow video BIOS ROM
  • 4B - Quiet-Boot start (not used in L440GX+)
  • 4E - Display copyright notice
  • 50 - Display processor(s) type and speed
  • 51 - EISA init (not used in L440GX+)
  • 52 - Reset and test keyboard controller (both warm and cold reset)
  • 54 - Set key click if enabled
  • 58 - Test for unexpected interrupts
  • 59 - Post display manager initialization (video screen error codes now visible)
  • 5A - Display prompt 'Press F2 to enter SETUP'
  • 5B - Disable processor L1 cache for memory test
  • 5C - Test RAM between 512KB and 640KB
  • 60 - Test extended memory (4MB to top of memory)
  • 62 - Test extended memory address lines
  • 64 - Jump to UserPatch1
  • 66 - Configure advanced cache registers
  • 67 - Initialize and register via SMM through APIC bus
  • 68 - Enable external and processor caches
  • 69 - Initialize SMI handler for all processors
  • 6A - Display external cache size
  • 6C - Display shadow message
  • 6E - Display non-disposable segments
  • 70 - Display error messages to video
  • 72 - Check for configuration errors
  • 74 - Test real time clock
  • 76 - Enable keyboard
  • 7C - Setup hardware interrupt vectors
  • 7E - Test coprocessor if present
  • 80 - Not used
  • 81 - Late POST core initialization of devices
  • 83 - Configure onboard hard disk controller
  • 84 - Clear interrupts from COM port detection
  • 85 - Initialize and detect PC compatible PnP ISA devices (parallel, serial, etc..)
  • 86 - Console redirection initialized
  • 87 - Configure MCD devices
  • 88 - Initialize BIOS Data Area, time-outs for detecting parallel, serial and HDD controller. Clear CMOS shutdown flag
  • 89 - Enable NMI
  • 8A - Initialize Extended BIOS Data Area
  • 8B - Detect and test for mouse and auxiliary device on keyboard controller
  • 8C - Initialize floppy controller
  • 8F - Get total # of hard drives and put in BDA
  • 90 - Initialize and detect hard disks
  • 91 - Program IDE hard drives (timing, PIO modes, etc...)
  • 92 - Jump to UserPatch2
  • 93 - Scan for User Flash ROMs. MP Table initialization (wake up secondary processor and halt it)
  • 95 - Install CD-ROM for boot
  • 97 - Fix-up MP table (checksum)
  • 98 - Search for option ROMs. One long, two short beeps on checksum failure of an option ROM
  • 99 - Check SMART hard drive
  • 9C - Setup Power Management (not used)
  • 9D - Enable security
  • 9E - Enable hardware interrupts
  • 9F - Save total # of hard drives (SCSI and ATA) in BDA
  • A0 - Set time of day
  • A2 - Check key lock
  • A4 - Initialize typematic rate
  • A8 - Erase F2 prompt
  • AA - Scan for F2 keystroke
  • AC - Initialize EMP port if selected. Remove COM2 from BDA if EMP is enabled. Enter SETUP
  • AE - Clear IN POST flag
  • B0 - Turn on secure boot if enabled (secure front panel, blank video, floppy write protect). Check for errors
  • B2 - POST done - prepare to boot Operating System
  • B4 - One short beep before boot
  • B5 - Display Quiet-Boot (not used)
  • BE - Clear screen
  • B6 - Check password (optional)
  • BC - Clear parity checkers
  • BA - Not used
  • B7 - ACPI configuration (table configuration in memory and BDA)
  • BD - Display Multi-Boot menu if ESC is hit
  • BF - Display system config summary (if enabled in CMOS)
  • C0 - Try to boot with Int19h. Return to video mode 3, disable PMM, return to real mode, disable gate A20, clears system memory, resets stack, invokes Int19h
  • C1 - Post error manager initialization
  • C2 - Initialize DMI tables
  • C3 - Log post errors with POST error manager and to SEL in BMC. Update VID bits and memory presence to BMC. Display and FRB errors (watchdog time-outs, bits or processor failures)
  • C4 - Initialize system flags in CMOS
  • C5 - Initialize GPNV areas in DMI
  • C7 - Prepare to boot to OS. Clean up graphics and PMM areas
  • D0 - Interrupt handler error
  • D2 - Unknown interrupt error
  • D4 - Pending interrupt error
  • D6 - Initialize option ROM error
  • D8 - Shutdown error
  • DA - Extended Block Move
  • DC - Shutdown 10 error
  • F4 - Exit SMI handler (secondary processor executed halt in SMI)
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